page 1 of 6 document no. 70-0186-04 www.psemi.com ?2005-2008 peregrine semiconductor corp. all rights reserved. 28-lead cqfp figure 2. package type the pe94302 is a high linearity, 6-bit ultracmos? rf digital step attenuator (dsa). this 50-ohm rf dsa covers a 31.5 db attenuation range in 0.5 db steps. it provides both parallel and serial cmos control interface. the pe94302 maintains high attenuation accuracy over frequency and temperature and exhibits very low insertion loss and power consumption. the pe94302 is optimized for commercial space applications. single event latch up (sel) is physically impossible and single event upset (seu) is better than 10-9 errors per bit / day. fabricated in peregrine?s ultracmos? technology, a patented variation of silicon-on-insulator (soi) technology on a sapphire substrate, the pe94302 offers excellent rf performance and intrinsic radiation tolerance. product specification 50 ? rf digital step attenuator for rad-hard space applications 6-bit, 31.5 db, dc ? 4.0 ghz product description figure 1. functional schematic diagram pe94302 features ? attenuation: 0.5 db steps to 31.5 db ? flexible parallel and serial programming interfaces ? 100 krads (si) total dose ? positive cmos control logic ? high attenuation accuracy and linearity over temperature and frequency ? low power - 100 a at 3.0v ? 50 ? impedance control logic interface parallel control serial control rf input rf output switched attenuator array 6 3 table 1. electrical specifications @ -40c temp +85c, 2.7v v dd 3.30v notes: 1. device linearity will begin to degrade below 1 mhz 2. maximum operating power = +12 dbm 3. specs are guaranteed to 2.2 ghz, characterized to 4.0 ghz parameter test conditions frequency min typical max units operation frequency dc - 4000 mhz insertion loss dc - 2.2 ghz 1.5 2.75 db attenuation accuracy 0.5 db - 8.0 db atten. dc - 1.0 ghz - (0.55 + 3.7% of atten. setting) + (0.55 + 3.7% of atten. setting) db 8.5 db - 31.5 db atten. + 0.9 0.5 db - 4.0 db atten. 1.0 - 2.2 ghz + (0.70 + 3.0% of atten. setting) 4.5 db - 31.5 db atten. + 0.9 0.5 db - 23.0 db atten. - (0.7+ 3.0% of atten. setting) 23.5 db - 31.5 db atten. - (0.6 + 9.0% of atten. setting) 1 db compression 1 mhz - 2.2 ghz 33 dbm input ip3 two-tone inputs 52 dbm return loss dc - 2.2 ghz 15 db rf input power (50 ? ) 12 dbm switching speed min to max atten. state 1 s
product specification pe94302 page 2 of 6 ?2005-2008 peregrine semiconductor corp. all rights reserved. document no. 70-0186-04 ultracmos? rfic solutions table 2. pin descriptions table 3. absolute maximum ratings electrostatic discharge (esd) precautions when handling this ultracmos? device, observe the same precautions that you would use with other esd- sensitive devices. although this device contains circuitry to protect it from damage due to esd, precautions should be taken to avoid exceeding the rate specified. exposed solder pad connection the exposed solder pad on the bottom of the package must be grounded for proper device operation. table 4. operating ranges figure 3. pin configuration (top view) symbol parameter/conditions min max units v dd power supply voltage -0.3 4.0 v v i voltage on any dc input -0.3 v dd + 0.3 v t st storage temperature range -65 150 c p in input power (50 ? ) 24 dbm v esd esd voltage (human body model) 500 v v ss negative power supply voltage (-v dd ) -4.0 0.3 v parameter min typ max units v dd power supply voltage 2.7 3.0 3.3 v i dd power supply current 250 a digital input high 0.7xv dd v digital input low 0.3xv dd v digital input leakage 1 a t op operating temperature range -40 85 c v ss power supply voltage -3.3 -3.0 -2.7 v i ss power supply current -500 a latch-up avoidance unlike conventional cmos devices, ultracmos? devices are immune to latch-up. switching frequency the pe94302 has a maximum 25 khz switching rate. pin no. pin name 1 c16 2 gnd 3 rf1 4 gnd 5 data 6 gnd 7 clk 8 le 9 v dd 10 gnd 11 rs1 12 gnd 13 rs2 14 v ss 15 reset 16 gnd 17 p/s 18 gnd 19 rf2 20 gnd 21 c8 22 c4 23 c2 24 gnd 25 gnd 26 gnd 27 c1 28 c0.5 paddle gnd description attenuation control bit, 16db ground connection rf port (note 1). ground connection serial interface data input ground connection serial interface clock input. latch enable input (note 2). power supply pin. ground connection redundant signal (note 3) ground connection redundant signal (note 3) negative supply voltage (note 4) reset (note 5) ground connection parallel/serial mode select. ground connection rf port (note 1). ground connection attenuation control bit, 8 db. attenuation control bit, 4 db. attenuation control bit, 2 db. ground connection ground connection ground connection attenuation control bit, 1 db. attenuation control bit, 0.5 db. ground connection pe94302 25 11 5 3 17 19 1 2 4 18 6 7 20 21 16 15 26 24 27 28 23 22 10 9 8 12 13 14 c16 gnd rf1 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd data clk le v dd rs1 rs2 v ss reset p/s rf2 c8 c4 c2 c1 c0.5 note 1: both rf ports must be held at 0 v dc or dc blocked with an external series capacitor. 2: latch enable (le) has an internal 100 k ? resistor to v dd. 3: must be tied to vdd or gnd under normal operation. 4: must be tied to external supply with v ss = -v dd 5: must be tied to gnd under normal operation exceeding absolute maximum ratings may cause permanent damage. operation should be restricted to the limits in the operating ranges table. operation between operating range maximum and absolute maximum for extended periods may reduce reliability.
product specification pe94302 page 3 of 6 document no. 70-0186-04 www.psemi.com ?2005-2008 peregrine semiconductor corp. all rights reserved. programming options parallel/serial selection either a parallel or serial interface can be used to control the pe94302. the p/s bit provides this selection, with p/s=low selecting the parallel interface and p/s=high selecting the serial interface. parallel mode interface the parallel interface consists of six cmos- compatible control lines that select the desired attenuation state, as shown in table 5. the parallel interface timing requirements are defined by figure 5 (parallel interface timing diagram), table 8 (parallel interface ac characteristics), and switching speed (table 1). for latched parallel programming the latch enable (le) should be held low while changing attenuation state control values, then pulse le high to low (per figure 5) to latch new attenuation state into device. for direct parallel programming, the latch enable (le) should be either pul led high or floated (see table 2, note 2). changing attenuation state control values will change device st ate to new attenuation. direct mode is ideal for m anual control of the device (using hardwire, switches, or jumpers). p/s c16 c8 c4 c2 c1 c0.5 attenuation state 0 0 0 0 0 0 0 reference loss 0 0 0 0 0 0 1 0.5 db 0 0 0 0 0 1 0 1 db 0 0 0 0 1 0 0 2 db 0 0 0 1 0 0 0 4 db 0 0 1 0 0 0 0 8 db 0 1 0 0 0 0 0 16 db 0 1 1 1 1 1 1 31.5 db table 5. truth table note: not all 64 possible combinations of c0.5-c16 are shown in table serial interface the serial interface is a 6-bit serial-in, parallel-out shift register buffered by a transparent latch. it is controlled by three cmos-compatible signals : data, clock, and latch enable (le). the data and clock inputs allow data to be serially entered into the shift register, a process that is independent of the state of the le input. the le input controls the latch. when le is high, the latch is transparent and t he contents of the serial shift register control the attenuator. when le is brought low, data in the shift register is latched. the shift register should be loaded while le is held low to prevent the attenuat or value from changing as data is entered. the le input should then be toggled high and brought low again, latching the new data. the timing for th is operation is defined by figure 4 (serial interface timing diagram) and table 7 (serial interface ac characteristics).
product specification pe94302 page 4 of 6 ?2005-2008 peregrine semiconductor corp. all rights reserved. document no. 70-0186-04 ultracmos? rfic solutions table 6. 6-bit attenuator serial programming register map table 8. parallel interface ac characteristics figure 5. parallel interface timing diagram table 7. serial interface ac characteristics figure 4. serial interface timing diagram le clock data msb lsb t lesup t sdsup t sdhld t lepw b5 b4 b3 b2 b1 b0 c16c8c4c2c1c0.5 lsb (last in) msb (first in) t pdsup t pdhld parallel data c16:c0.5 le t lepw symbol parameter min max unit f clk serial data clock frequency (note 1) 10 mhz t clkh serial clock high time 30 ns t clkl serial clock low time 30 ns t lesup le set-up time after last clock falling edge 10 ns t lepw le minimum pulse width 30 ns t sdsup serial data set-up time before clock rising edge 10 ns t sdhld serial data hold time after clock falling edge 10 ns note: f clk is verified during the functi onal pattern test. serial programming sections of the fu nctional pattern are clocked at 10 mhz to verify fclk specification. symbol parameter min max unit t lepw le minimum pulse width 10 ns t pdsup data set-up time before rising edge of le 10 ns t pdhld data hold time after falling edge of le 10 ns v dd = 3.0 v, -40 c < t a < 85 c, unless otherwise specified v dd = 3.0 v, -40 c < t a < 85 c, unless otherwise specified
product specification pe94302 page 5 of 6 document no. 70-0186-04 www.psemi.com ?2005-2008 peregrine semiconductor corp. all rights reserved. figure 8. insertion loss figure 6. input return loss vs. frequency figure 7. output return loss vs. frequency typical performance data @ 25c, v dd = 3.0 v figure 9. attenuation setting vs. frequency
product specification pe94302 page 6 of 6 ?2005-2008 peregrine semiconductor corp. all rights reserved. document no. 70-0186-04 ultracmos? rfic solutions figure 10. attenuation error vs. frequency figure 11. attenuation error vs. setting typical performance data @ 25c, v dd = 3.0 v figure 12. iip3 vs. frequency figure 13. 1 db compression vs. frequency
product specification pe94302 page 7 of 6 document no. 70-0186-04 www.psemi.com ?2005-2008 peregrine semiconductor corp. all rights reserved. table 9. ordering information order code part marki ng description package shipping method 94302-01 94302 pe94302-28cqfp-50b engineering samples 28-lead cqfp 25 count trays 94302-11 94302 pe94302-28cqfp-50b production units 28-lead cqfp 25 count trays 94302-00 pe94302-ek pe94302 evaluation kit evaluation board 1 / box figure 14. package drawing (dimensions in inches) 28-lead cqfp
product specification pe94302 page 8 of 6 ?2005-2008 peregrine semiconductor corp. all rights reserved. document no. 70-0186-04 ultracmos? rfic solutions sales offices the americas peregrine semiconductor corporation 9380 carroll park drive san diego, ca 92121 tel: 858-731-9400 fax: 858-731-9499 europe peregrine semiconductor europe batiment maine 13-15 rue des quatre vents f-92380 garches, france tel: +33-1-4741-9173 fax : +33-1-4741-9173 for a list of representatives in your area, please refer to our web site at: www.psemi.com data sheet identification advance information the product is in a formative or design stage. the data sheet contains design target specifications for product development. specifications and features may change in any manner without notice. preliminary specification the data sheet contains preliminary data. additional data may be added at a later date. peregrine reserves the right to change specifications at an y time without notice in order to supply the best possible product. product specification the data sheet contains final dat a. in the event peregrine decides to change the specifications, peregrine will notify customers of the intended changes by issuing a dcn (document change notice). the information in this data sheet is believed to be reliable. however, peregrine assumes no liability for the use of this information. use shall be entirely at the user?s own risk. no patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. peregrine?s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the peregrine product could create a situation in which persona l injury or death might occur. peregrine assumes no liability for damages, including consequential or incidental dam ages, arising out of the use of its products in such applications. the peregrine name, logo, and utsi are registered trademarks and ultracmos and harp are trademarks of peregrine semiconductor corp. space and defense products americas: tel: 858-731-9453 europe, asia pacific: 180 rue jean de guiramand 13852 aix-en-provence cedex 3, france tel: +33-4-4239-3361 fax: +33-4-4239-7227 peregrine semiconductor, asia pacific (apac) shanghai, 200040, p.r. china tel: +86-21-5836-8276 fax: +86-21-5836-7652 peregrine semiconductor, korea #b-2607, kolon tripolis, 210 geumgok-dong, bundang-gu, seongnam-si gyeonggi-do, 463-943 south korea tel: +82-31-728-3939 fax: +82-31-728-3940 peregrine semiconductor k.k., japan teikoku hotel tower 10b-6 1-1-1 uchisaiwai-cho, chiyoda-ku tokyo 100-0011 japan tel: +81-3-3502-5211 fax: +81-3-3502-5213
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